16 Mbit LPC Flash
SST49LF160C
Advance Information
Load Enable
The Load Enable pin (LD#), is an input pin which when low,
indicates the host is loading data in an AAI programming
cycle. Data is loaded in the SST49LF160C at the rising
edge of the clock. If LD# is high, it signals the AAI interface
that the host is terminating the command. LD# low/high
switches the RY/BY# output from buffer free flag to pro-
gramming complete flag (see Table 18).
No Connection (NC)
LPC MODE
Device Operation
The SST49LF160C supports Single-Byte LPC Memory
Read and Write cycle types as defined in Low Pin Count
Interface Specification. Table 2 shows the size of transfer
supported by the SST49LF160C.
TABLE 2: Transfer Size Supported
Cycle Type Size of Transfer
These pins are not connected internally.
LPC Memory Read
1 Byte
DESIGN CONSIDERATIONS
LPC Memory Write
1 Byte
T2.0 1315
SST recommends a high frequency 0.1 μF ceramic capac-
itor to be placed as close as possible between V DD and
V SS less than 1 cm away from the V DD pin of the device.
Additionally, a low frequency 4.7 μF electrolytic capacitor
from V DD to V SS should be placed within 1 cm of the V DD
pin. If you use a socket for programming purposes add an
additional 1-10 μF next to each socket.
The RST# pin must remain stable at V IH for the entire dura-
tion of an Erase operation. WP#/AAI must remain stable at
V IH for the entire duration of the Erase and Program opera-
tions for non-Boot Block sectors. To write data to the top
Boot Block sectors, the TBL# pin must also remain stable
at V IH for the entire duration of the Erase and Program
operations.
MODE SELECTION
The SST49LF160C flash memory device operates in two
distinct interface modes: the LPC mode and the Auto
The LPC mode uses a 5-signal communication interface:
one control line, LFRAME#, which is driven by the host to
start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used
to communicate cycle type, cycle direction, ID selection,
address, data and sync fields. The device enters standby
mode when LFRAME# is taken high and no internal opera-
tion is in progress.
The host drives LFRAME# signal from low-to-high to cap-
ture the start field of a LPC cycle. On the cycle in which
LFRAME# goes inactive, the last latched value is taken as
the START value. The START value determines whether
the SST49LF160C will respond to a LPC Memory Read/
Write cycle type as defined in Table 3.
TABLE 3: LPC Memory Cycles START Field
Definition
START
Value Definition
Address Increment (AAI) mode. The WP#/AAI pin is used
0000
Start of an LPC memory cycle. The direction
to set the interface mode selection. The device is in AAI
mode when the WP#/AAI pin is set to the Supervoltage V H
(9±0.5V), and in the LPC mode when the WP#/AAI is set to
V IL /V IH. The mode selection must be configured prior to
device operation.
(Read or Write) is determined by the second field
of the LPC cycle.
T3.1 1315
See following sections on details of LPC Memory cycle
types (Tables 4 and 5). Two-cycle Program and Erase
command sequences are used to initiate LPC Memory
Program and Erase operations. See Table 8 for a listing of
Program and Erase commands.
?2006 Silicon Storage Technology, Inc.
11
S71315-00-000
4/06
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相关代理商/技术参数
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